The present invention relates to a drive circuit and a drive circuit system, and more specifically to a drive circuit and a drive circuit system used in a driver or a buffer which constitutes an output stage of a driving circuit for a capacitive load exemplified by a liquid crystal display (LCD).
As a typical example of a drive circuit for a capacitive load, a liquid crystal display (LCD) will be now described. In general, a display section of the liquid crystal display of an active matrix driving type includes a semiconductor substrate having transparent pixel electrodes and thin film transistors (TFT) formed thereon, an opposing substrate having a single transparent common electrode formed to cover the whole of a surface of the substrate, and a liquid crystal encapsulated between the two substrates which are located to oppose each other, separately from each other. By controlling the TFTs having a switching function, a predetermined voltage is applied to selected pixel electrodes so that a transmittance of the liquid crystal is changed by a potential difference between each pixel electrode and the opposing common electrode.
On the semiconductor substrate, data lines for supplying a plurality of different level voltages (gradation voltages) to be selectively applied to each pixel electrode, and scan lines for supplying a switching control signal for each TFT, are located. The data lines become a large capacitive load because of a liquid crystal capacitance between the data lines and the opposing common electrode and a capacitance between the data lines and the scan lines that intersect each other. Since the gradation voltage is applied through the data line to each pixel electrodes, and since the gradation voltages are written to all the pixels connected to the data lines during each one frame period, a data line drive circuit has to rapidly drive a corresponding data line which is a large capacitive load.
As mentioned above, the data line drive circuit is required to rapidly drive a corresponding data lines having a large capacitance with a high voltage precision. In order to meet with this demand, various data line drive circuits have been developed. Of the various data line drive circuits developed until now, a circuit that has enabled a high voltage precision output and a rapid driving is a drive circuit including a driver (buffer) section formed of an operational amplifier. A typical and simplest example will be shown in FIG. 16.
The operational amplifier shown in FIG. 16 is in the form of a voltage follower, capable of outputting, as an output voltage Vout, a voltage equal to an input voltage Vin. The shown operational amplifier is constituted of a differential amplifier stage 610 and an output amplifier stage 620. The differential amplifier stage 610 includes a current control circuit 601, PMOS transistors 603 and 604 having the same characteristics, and NMOS transistors 605 and 606 having the same characteristics, which are connected as shown.
In brief, the NMOS transistors 605 and 606 have respective gates connected in common, and respective sources connected in common to a power supply terminal T14. A drain of the NMOS transistor 606 is connected to the gate of the NMOS transistor 606. The PMOS transistors 603 and 604 have respective sources connected in common. A gate of the PMOS transistor 603 is connected to an input terminal T1 to receive the input voltage Vin. A drain of the PMOS transistor 603 is connected to a drain of the NMOS transistor 605. A gate of the PMOS transistor 604 is connected to an output terminal T2 for outputting the output voltage Vout.
A drain of the PMOS transistor 604 is connected to the drain of the NMOS transistor 606. The current control circuit 601 is connected between a power supply terminal T13 and the common-connected sources of the PMOS transistors 603 and 604.
On the other hand, the output amplifier stage 620 includes a current control circuit 602, an NMOS transistor 607 and a capacitor 608, connected as shown. The current control circuit 602 is connected between a power supply terminal T11 and the output terminal T2. The NMOS transistor 607 has a drain connected to the output terminal T2, a source connected to a power supply terminal T12, and a gate connected to the common-connected drains of the PMOS transistor 603 and the NMOS transistor 605. The capacitor 608 is connected between the gate of the NMOS transistor 607 and the output terminal T2. Here, currents controlled by the current control circuits 601 and 602 are called I61 and I62, respectively. A voltage VDD is supplied to the power supply terminals T11 and T13, and a voltage VSS is supplied to the power supply terminals T12 and T14. In addition, the output terminal T2 is connected to the data line, which is a capacitive load.
Since the output voltage Vout is fed back to the differential amplifier stage 610, namely, since the output voltage Vout is applied to the gate of the PMOS transistor 604, the operational amplifier shown in FIG. 16 has a construction having a voltage amplification factor of xe2x80x9c1xe2x80x9d (one) and a high current supplying capacity (voltage follower).
In operation, when the output voltage Vout is lower than the input voltage Vin, a gate voltage of the NMOS transistor 607 is lowered, so that the NMOS transistor 607 is temporarily brought into an off condition, with the result that the output voltage Vout is pulled up by the current I62 supplied through the current control circuit 602. On the other hand, when the output voltage Vout is higher than the input voltage Vin, a gate voltage of the NMOS transistor 607 is elevated, so that the output voltage Vout is pulled down by action of the NMOS transistor 607. At this time, since the NMOS transistors 605 and 606 act to flow the same current through the respective drain-source paths, the output voltage Vout is attenuated and rapidly converged to the input voltage Vin. In the operation, a phase compensation is carried out by the capacitor 608 so that oscillation is prevented.
In the above mentioned operation, a designated or selected gradation voltage is applied as the input voltage Vin during each outputting period, and the operational amplifier can drive the data line connected to the output terminal T2 and having a large capacitance, by the gradation voltage with a high current supplying capacity.
In addition, the operational amplifier can drive the data line, by action of an impedance conversion, independently of a current supplying capacity of an external circuit supplying the input voltage Vin.
However, since the operational amplifier shown in FIG. 16 (voltage follower circuit) has a feed-back structure, oscillation often occurs, and therefore, it is necessary to provide the means such as a phase compensation capacitor for preventing the oscillation. Furthermore when the operational amplifier is integrated as an integrated circuit, the phase compensation capacitor often requires a large occupying chip. Therefore, when a number of operational amplifiers are built in a single integrated circuit, a required area of the integrated circuit becomes large, with the result that a production cost adversely increases.
Accordingly, it is an object of the present invention to overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a drive circuit having a simple circuit construction which can be constituted of only transistors, and capable of stably operating with no oscillation, for rapidly driving a load with a high precision voltage output.
Still another object of the present invention is to provide a drive circuit and a drive circuit system, which can reduce the production cost when a number of drive circuits are integrated as an integrated circuit.
The above and other objects of the present invention are achieved in accordance with the present invention by a drive circuit comprising a level converting means for level-converting an input voltage into a first voltage, a first transistor having a gate connected to receive the first voltage and a source for outputting an output voltage pursuant to the input voltage, a first current control means for controlling a current flowing through a drain-source path of the first transistor so that the first transistor operates in a source follower fashion, the level converting means including a second transistor of the same conductivity type as that of the first transistor. Preferably, the second transistor has a source connected to receive the input voltage, and a drain and a gate connected in common for outputting the first voltage, and the level converting means also includes a second current control means for controlling a current flowing through a drain-source path of the second transistor.
According to another aspect of the present invention, there is provided a drive circuit comprising a first power supply terminal, an input terminal for receiving an input voltage, an output terminal for outputting an output voltage, a first transistor having a source connected to the input terminal and a drain and a gate connected in common, a second transistor of the same conductivity type as that of the first transistor, the second transistor having a drain connected to the first power supply terminal, a source connected to the output terminal, and a gate connected to receive a voltage equal to a gate voltage of the first transistor, a first current control means for controlling a current flowing through a drain-source path of the first transistor, and a second current control means for controlling a current flowing through a drain-source path of the second transistor.
In this drive circuit, the first current control means can include a first current control circuit connected between a second power supply terminal and the drain of the first transistor, and the second current control means can include a second current control circuit connected between the output terminal and a third power supply terminal. Furthermore, a third current control circuit can be connected between the input terminal and a fourth power supply terminal.
Preferably, the drive circuit can further include at least a first switch connected in series with the first transistor between the input terminal and the second power supply terminal and on-off controlled for cutting off a current flowing between the input terminal and the second power supply terminal, a second switch connected in series with second current control circuit between the output terminal and the third power supply terminal and on-off controlled for cutting off a current flowing between the output terminal and the third power supply terminal, a third switch connected in series with the third current control circuit between the input terminal and the fourth power supply terminal and on-off controlled for cutting off a current flowing between the input terminal and the fourth power supply terminal, and a fourth switch connected in series with the second transistor between the output terminal and the first power supply terminal and on-off controlled for cutting off a current flowing between the output terminal and the first power supply terminal.
In addition, the drive circuit can further include a first precharging means for precharging the output terminal to at least one predetermined voltage. In this connection, the drive circuit can further include a second precharging means for precharging the gate of the first transistor to a first predetermined voltage.
In another embodiment of the drive circuit, the first current control circuit includes a first current controlling transistor having a drain-source path connected between a second power supply terminal and the drain of the first transistor, and the second current control circuit includes a second current controlling transistor having a drain-source path connected between the output terminal and a third power supply terminal. The second current controlling transistor is of the conductivity type different from that of the first current controlling transistor. The third current control circuit includes a third current controlling transistor having a drain-source path connected between the input terminal and a fourth power supply terminal. The third current controlling transistor is of the same conductivity type as that of the second current controlling transistor. The drive circuit further includes a bias circuit having a first bias transistor and a second bias transistor connected in series. The first bias transistor is of the conductivity type different from that of the second bias transistor. The first bias transistor and the second bias transistor have a drain-source path current equal in magnitude to each other. The first bias transistor is of the same conductivity type as that of the first current controlling transistor, and has the same gate-source voltage as that of the first current controlling transistor. The second bias transistor is of the same conductivity type as that of the second and third current controlling transistors, and has the same gate-source voltage as that of the second and third current controlling transistors.
According to a third aspect of the present invention, there is provided a drive circuit system comprising an input terminal for receiving an input voltage, an output terminal for outputting an output voltage, first and second drive circuits each connected to the input terminal and the output terminal,
the first drive circuit including:
a first n-channel transistor having a source connected to the input terminal and a drain and a gate connected in common;
a second n-channel transistor having a drain connected to a first power supply terminal, a source connected to the output terminal, and a gate connected to receive a voltage equal to a gate voltage of the first n-channel transistor;
a first current control means for controlling a drain-source path current of the first n-channel transistor; and
a second current control means for controlling a drain-source path current of the second n-channel transistor,
the second drive circuit including:
a first p-channel transistor having a source connected to the input terminal and a drain and a gate connected in common;
a second p-channel transistor having a drain connected to a second power supply terminal, a source connected to the output terminal, and a gate connected to receive a voltage equal to a gate voltage of the first p-channel transistor;
a third current control means for controlling a drain-source path current of the first p-channel transistor, and
a fourth current control means for controlling a drain-source path current of the second p-channel transistor.
In this drive circuit system, the first current control means can include a first current control circuit connected between a third power supply terminal and the drain of the first n-channel transistor, and the second current control means can include a second current control circuit connected between the output terminal and a fourth power supply terminal. In addition, the third current control means can include a third current control circuit connected between a fifth power supply terminal and the drain of the first p-channel transistor, and the fourth current control means includes a fourth current control circuit connected between the output terminal and a sixth power supply terminal.
Preferably, the first drive circuit can further include a fifth current control circuit connected between the input terminal and a seventh power supply terminal, and the second drive circuit can include a sixth current control circuit connected between the input terminal and an eighth power supply terminal.
Furthermore, the first drive circuit can further include at least a first switch connected in series with the first n-channel transistor between the input terminal and the third power supply terminal and on-off controlled for cutting off a current flowing between the input terminal and the third power supply terminal, a second switch connected in series with the second current control circuit between the output terminal and the fourth power supply terminal and on-off controlled for cutting off a current flowing between the output terminal, and the fourth power supply terminal, a third switch connected in series with the fifth current control circuit between the input terminal and the seventh power supply terminal and on-off controlled for cutting off a current flowing between the input terminal and the seventh power supply terminal, and a fourth switch connected in series with the second n-channel transistor between the output terminal and the first power supply terminal and on-off controlled for cutting off a current flowing between the output terminal and the first power supply terminal. On the other hand, the second drive circuit can further include at least a fifth switch connected in series with the first p-channel transistor between the input terminal and the fifth power supply terminal and on-off controlled for cutting off a current flowing between the input terminal and the fifth power supply terminal, a sixth switch connected in series with the fourth current control circuit between the output terminal and the sixth power supply terminal and on-off controlled for cutting off a current flowing between the output terminal and the sixth power supply terminal, a seventh switch connected in series with the sixth current control circuit between the input terminal and the eighth power supply terminal and on-off controlled for cutting off a current flowing between the input terminal and the eighth power supply terminal, and an eighth switch connected in series with the second p-channel transistor between the output terminal and the second power supply terminal and on-off controlled for cutting off a current flowing between the output terminal and the second power supply terminal.
More preferably, the drive circuit system can further include a first precharging means for precharging the output terminal to at least one predetermined voltage. In this connection, the drive circuit system can further include a second precharging means for precharging the gate of the first n-channel transistor to a first predetermined voltage, and a third precharging means for precharging the gate of the first p-channel transistor to a second predetermined voltage.
According to a fourth aspect of the present invention, there is provided a drive circuit apparatus comprising:
a bias circuit including comprising a first transistor of a first conductivity type having a source connected to a first power supply terminal and a gate connected to receive a controlling voltage, and a second transistor of a second conductivity type opposite to the first conductivity type, the second transistor having a source connected to a second power supply terminal, and a gate and a drain connected in common to a drain of the first transistor so that the same drain-source current flows through the first transistor and the second transistor; and
a drive circuit including at least one first current control transistor of the first conductivity type having the same device size as that of the first transistor, the at least one first current control transistor having a gate and a source connected to a gate and the source of the first transistor, respectively, and at least one second current control transistor of the second conductivity type having the same device size as that of the second transistor, the at least one second current control transistor having a gate and a source connected to the gate and the source of the second transistor, respectively.
With the above mentioned arrangement, a gate-source voltage of the first transistor is unambiguously determined by a drain-source current of the first transistor. Therefore, if an input voltage Vin is applied to the source of the first transistor, the gate voltage of the first transistor becomes a voltage that is deviated from the input voltage Vin by the gate-source voltage of the first transistor. On the other hand, since the drain of the second transistor receives the power supply voltage and the gate of the second transistor receives the voltage equal to the gate voltage of the first transistor, the second transistor operates in a source follower fashion. Therefore, if the drain-source current of the second transistor is controlled, the gate-source voltage of the second transistor is unambiguously determined, so that an output voltage Vout obtained from the source of the second transistor becomes stable at a voltage which is deviated from the gate voltage of the second transistor by the gate-source voltage of the second transistor.
Thus, by controlling the drain-source currents of the first and second transistors, it is possible to obtain the output voltage Vout pursuant to the input voltage Vin. In addition, when the input voltage Vin varies, the output voltage Vout rapidly changes to a voltage pursuant to the input voltage Vin, by action of the source-follower operation of the second transistor.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.